Pooja V. Shete, Mahantesh P. Mattada, Hansraj Guhilot and Deshmukh S. C
Line multiplier is a novel way of multiplication. In Digital signal processing operation multiplication is heavily used arithmetic operation and performance of processor depends on multiplier performance. So designing a low power multiplier is essential. In this paper line multiplier is implemented which is adder-less so easy to implement. Also no need to select or design an adder circuitry. In this paper line multiplier is designed and implemented on FPGA platform using Spartan 3 FPGA kit.
Multiplier, FPGA.