G.Prathipa, K.Muthumeena
The need for security has been increasing day by day. The Advance Encryption Standard (AES) Algorithm is used for encryption and decryption purpose and it is one of the most popular Algorithm used in symmetric key cryptography. The AES specifies a FIPS approved cryptographic Algorithm that can be used to protect electronic data. The existing algorithm uses more number of transistors to implement the S-Box and INV S-Box. The heart of the S-Box is Multiplicative inverse unit. It requires eight XOR gates for Squaring Operation in GF (24) and Multiplication with Constant block and there are two XOR gates and one AND gate in the critical path of Multiplicative in GF (22) block. CMOS logic is used to design the logic gates and mux. The Squaring Operation in GF (24) and Multiplication with Constant block requires 48T and Multiplicative in GF (22) block requires 66T. This Architecture of Multiplicative inverse unit increases the area, power, critical path and transistor. In the proposed work, the compact S-Box has been designed by using reduced Multiplicative inverse unit.GDI (Gate Diffusion Input) logic is used to design the S-Box. It will be designed by reducing the number of transistors in S-Box. The TANNER EDA is used to design the proposed S-Box.
S-box, Composite field arithmetic, AES encryption, GDI